The present invention relates, in general, to the field of integrated circuit memory devices. More particularly, the present invention relates to a double data rate ("DDR") synchronous dynamic random access memory ("SDRAM") device which incorporates a static random access memory ("SRAM") cache per memory bank.
As the performance of computer central processing units ("CPUs") has increased dramatically in recent years, this performance improvement has far exceeded that of any corresponding increase in the performance of computer main memory. Typically, main memory has been made up of numbers of asynchronous DRAM integrated circuits and it was not until the introduction of faster SRAM cache memory that the performance of systems with DRAM main memory improved. This performance improvement was achieved by making a high speed locally-accessed copy of memory available to the CPU so that even during memory accesses, the CPU would not always need to operate at the slower speeds of the system bus and the main memory DRAM. This method of copying memory is referred to as "caching" a memory system and is a technique made possible by virtue of the fact that much of the CPU accesses to memory is directed at localized memory address regions. Once such a region is copied from main memory to the cache, the CPU can access the cache through many bus cycles before needing to refresh the cache with a new memory address region. This method of memory copying is advantageous in memory Read cycles which, in contrast to Write cycles, have been shown to constitute 90% of the external accesses' of the CPU.
As mentioned previously, the most popular hardware realization of a cache memory employs a separate high-speed SRAM cache component and a slower but less expensive DRAM component. A proprietary Enhanced DRAM (EDRAM.RTM.) integrated circuit memory device, developed by Enhanced Memory Systems, Inc., assignee of the present invention, integrates both of these memory elements on one chip along with on-chip tag maintenance circuitry to further enhance performance of computer main memory over separate SRAM and DRAM components. Details of the EDRAM device are disclosed and claimed in U.S. Pat. Nos.: 5,699,317 issued Dec. 16, 1997 and 5,721,862 issued Feb. 24, 1998, both assigned to Enhanced Memory Systems, Inc., the disclosures of which are specifically incorporated herein by this reference.
SDRAMs differ from earlier asynchronous DRAM devices by incorporating two or more memory banks per device and by providing a simple, synchronously clocked interface in lieu of separate asynchronous clocking and discrete row and column access control lines. These differences result in a relatively higher data bandwidth and potentially faster access times for computer main memory which is particularly important with current and anticipated memory intensive multimedia and graphics applications.
The DRAM industry has also developed a double data rate version of the synchronous DRAM that doubles the peak data rate of the SDRAM by clocking data on both edges of the clock. Double data rate SDRAMs utilize a bi-directional data strobe to clock data to and from the memory device. The data strobe is clocked at the same time as the data and propagates over a bus which is designed to be substantially the same length and have the same capacitive loading as the data bus to minimize skew between the data strobe and the data signals.
However, like the SDRAM, the DDR SDRAM exhibits a relatively slow DRAM latency for activating the DRAM bank (row-to-column delay time "t.sub.RCD ") and accessing data from the sense amplifiers (column address strobe "CAS" latency). Since burst read data is accessed from the sense amplifiers, the row must remain activated until the burst is completed. This increases the latency to access another row on the next burst. The combination of long row access latency (t.sub.RCD +CAS latency) together with long page miss latency (precharge time "t.sub.RP " plus tRCD and CAS latency) results in poor bus efficiency when frequent page misses on random accesses occur. In addition, the current DDR SDRAM requires the bus to be idle (or unused) during all DRAM refresh operations thereby further degrading performance.